High Performance Asynchronous Pipelines

Computer Engineering electronics Engineering Civil Engineering

ONE OF THE FOUNDATIONS of high-performance digital system design is the use of pipelining. In synchronous systems, for several decades, pipelining has been the fundamental technique used to increase parallelism and hence boost system throughput whether for high-performance processors, multimedia and graphics units, or signal processors. This article provides an overview of pipelining in asynchronous, or clockless, digital systems. We do not attempt an exhaustive coverage, but rather introduce the basics of several leading representative styles. These pipelines naturally fall into two classes: those that use static logic versus those that use dynamic logic for the data path. Each class tends to use a distinct approach for its control and data storage. For static logic, we introduce the classic micropipeline of Sutherland,1 along with two highperformance variants: Mousetrap2 (which uses a standard cell design) and GasP3 (which uses a custom design). For dynamic logic, we present the classic PS0 pipeline of Williams and Horowitz,4,5 along with two high-performance variants: the precharge half-buffer (PCHB) pipeline6 (which provides greater timing robustness) and the high-capacity (HC) pipeline7 (which provides double the storage capacity). We also briefly discuss design tradeoffs, performance evaluation, systemlevel analysis and optimization techniques, CAD tool support, testing, and recent industrial and academic applications. loading..